1. Field of the Invention
Aspects of the present invention relate to a memory test device and a memory test method, and more particularly to a memory test device comprising an extension register and a memory test method using the same.
2. Description of the Related Art
In general, detection of errors in a memory to thereby reduce the error rate is an important process for memory producers and electronic apparatus producers producing and selling their products employing the memories produced by the memory producers. As memory has had a small capacity in the past, a memory test process was not as time consuming in the entire production process as compared to other production processes.
However, the storage capacity of a memory has exponentially increased owing to recent development in hardware technology. Thus, an error test in the memory has become an important issue, because error testing is directly associated with the productivity of the memory industry. For example, if it takes 20 minutes to detect errors in a 128 MB memory, the time to detect errors in a 1 GB memory would be simply computed at 160 minutes. As CPU performance, memory access time, bandwidth, etc. have increased, it would be difficult to assert that the testing process simply takes eight times longer. However, the test time would be approximately 2-5 times or longer.
A conventional memory test widely used and commercially available at present is executed in the unit of 32 bits (4 bytes). As the 32-bit test employs the most universalized computer command language and the same data processing unit, it is excellent in compatibility and universality. However, where the test bit number is increased in order to reduce the memory test time, a separate test device capable of supporting the increased data and command language is required.